In the field of Metal Oxide Semiconductor (MOS) technology, the trend is toward increasingly complex levels of integration. Monolithic MOS devices incorporating more than 1,000,000 gate equivalents on an entire silicon wafer will soon be a reality. Because of the defects inherent in both the silicon crystal structure and in the component manufacturing process, wafer scale architectures will be based on built-in self-test functions which internally identify and bypass defective portions of the wafer and interconnect the useable ones. Component redundancy will be used to insure that the wafer is useable after defective components have been bypassed.
Several obstacles must be overcome before wafer-scale integration (WSI) can become a practical reality. One of the major problems with WSI is that when paralleling functionally-equivalent devices to increase the number of possibilities of a working portion of the device, it is necessary to connect in parallel the output bit lines of each of those devices. Thus, for example, the output line of the parallel arrangement which bears the first bit of a word must be connected to the first-bit output terminals of each of the other functionally-equivalent devices. It is therefore necessary to use an output architecture which allows the output logic level of a selected device to be unaffected by connection to the output terminals of the other functionally-equivalent devices which have not been selected. This task is commonly accomplished through the use of the standard three-state, dual-transistor line driver shown in FIG. 1. This device has a pair of input lines, 1 and 2. The values input to lines 1 and 2 determine the value of output O, which will be 1 when connected through transistor PQ to the voltage source V, O when connected to connection to ground G through transistor NQ, and O when connected to both V and G through transistors PQ and NQ, respectively. O is isolated from both voltage source V and connection to ground G. This isolated state is commonly referred to as the "tri-state".
The logic table for the standard line driver of FIG. 1 is as follows:
______________________________________ Inputs: 1 2 Output (O) ______________________________________ 0 0 1 0 1 0 (voltage source and output grounded) 1 0 Tri-state (O isolated from V and G) 1 1 0 ______________________________________
The standard, three-state line driver has become a major point of failure in WSI architecture because it is used almost exclusively as a driver at the boundary of functional blocks, where it is connected through its output to a large WSI system bus. Failure of the standard line driver--typically caused by a breakdown in one of the two transistors--will almost invariably destroy the WSI system bus by either grounding it or shorting it to the driver voltage source. The failure modes of the standard line driver is as follows:
______________________________________ Failure of: Effect on PQ NQ Output (O) ______________________________________ no yes O grounded yes no O shorted to voltage source ______________________________________
Given the destructive nature of a failed standard line driver, there is a crucial need for an improved three-state line driver which, given a failure of a single transistor therein, will not produce a short between either the voltage source or ground and the bus output.